Energy Efficient and Timing Error Mitigation Circuit Design Based on Clock Adjustment

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Fathimath Ashitha C., N. Arun Prasath, Dr. N. Kaleeswari, P. Eswari, Dr. Mary Praveena S., Dr. P. Gowtham

Abstract

Due to the high rate of mistake occurrence on semiconductors, timing inaccuracy is currently attracting more attention. Since the latest semiconductor operates at a high frequency and has a low supply voltage, even little external disturbances can damage the timing margin between subsequent clocks. Different strategies have been introduced to cope with a timing error. Existing approaches to reduce a timing issue, however, are primarily focused on time-delaying mechanisms and overly complex operations, resulting in a timing hazard on clock-based systems as well as hardware overhead. The suggested work shows a new timing-error-tolerant method that can quickly fix a timing error using a simple methodology. The proposed technique can recover a timing error without losing time in a clock-based system by altering a clock in a flip-flop. In addition, in order to reduce power consumption in stages where no operation is carried out. To decrease the number of undesired transitions, a clock gating technique is used.  Look-Ahead Clock Gating (LACG) generates each FF's clock enabling signals one cycle ahead of time, and use the current cycle data of the FFs on which it depends. By allocating a whole clock cycle for the enabling signals to be computed and propagated to their gaters, it avoids the severe timing limitations of earlier techniques.  In comparison to previous timing-error-tolerant systems that can recover the error instantaneously, the suggested system has a minimal hardware overhead due to the compact mechanism. The proposed circuit was fully simulated by addressing PVT changes to verify our strategy. It was also used in a number of benchmark designs, including a microprocessor.

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